On-chip inductors and transformers are key passive components in radio frequency/millimeter wave integrated circuits (RF/MMICs). On-chip differential inductors are highly desirable for any circuits with differential structures, such as amplifiers, mixers, voltage controlled oscillators (VCOs), and phase-locked loops (PLLs)/synthesizers, frequency dividers and many others.
Some known on-chip inductor and transformer devices include:    (1) Single-ended multi-layer on-chip inductors;    (2) Planar on-chip differential inductors which do not use multiple metal layers;    (3) Planar on-chip transformers which do not use multiple metal layers;    (4) Multilayer balun transformers realizing single-ended to balanced conversion.
U.S. Pat. No. 6,759,937 B2 to Kyriazidou discloses an on-chip differential multi-layer inductor that in one embodiment includes a first partial winding on a first layer, a second partial winding on the first layer, a third partial winding on a second layer, a fourth partial winding on the second layer, and an interconnecting structure. The first and second partial windings on the first layer are operably coupled to receive a differential input signal. The third and fourth partial windings on the second layer are each operably coupled to a center tap. The interconnecting structure couples the first, second, third and fourth partial windings such that the first and third partial windings form a winding that is symmetrical about the center tap with a winding formed by the second and fourth partial windings. The first, second, third and fourth partial windings are for the most part, but not entirely vertically aligned and not symmetric about a center line (see FIGS. 4 for the multiple layer differential inductor embodiment and 6 for another embodiment, the multiple turn, multiple layer differential inductor). In inductors, what is needed is magnetic coupling instead of electrical coupling between the windings. Vertical alignment makes the electrical coupling high through the capacitance between windings.
U.S. Pat. No. 6,707,367 B2 to Castaneda, et al. discloses an on-chip multiple tap transformed balun that includes a first winding and a second winding having two portions. Castaneda et al. disclose a single-layer structure in which multiple windings are placed on the same layer. This type of structure has a relatively large size. Cost and the low self resonant frequency are issues due to the large size. The large size is expensive because chip real estate is expensive. For this reason, much effort has been devoted to shrinking the technology from micron to sub-micron to deep sub-micron scales.
U.S. Pat. No. 6,603,383 to Gevorgian, et al. discloses a multilayer, balanced-unbalanced signal transformer comprising a first coil and a second coil providing at least one balanced signal port at one side of the balun transformer and an unbalanced signal port at another side of the balun transformer. The windings of the coils are vertically aligned. In transformers, what is needed is magnetic coupling instead of electrical coupling between the primary and the secondary coils. Vertical alignment makes the electrical coupling high through the capacitance between windings.
Although the devices disclosed in the patents mentioned above offer advantages, they may still be improved upon. For instance, the device disclosed in the '367 patent uses multiple windings on the same layer (called a single-layer structure). The relatively large size of this device raises issues of cost and low self resonant frequency. The devices of the '383 and '937 patents use windings that are vertically aligned. However, in transformers magnetic coupling is preferable over electrical coupling between the primary and the secondary coils, but vertical alignment results in high electrical coupling due to the capacitance between windings.
It is desirable to design and fabricate on-chip inductors and transformers with characteristics of small size, high quality factor (Q factor), large inductance, high coupling efficiency and high self-resonating frequency that are improved from the references and the known devices described above. In silicon based integrated circuits where the substrate is lossy, it is especially important to make on-chip inductors and transformers consume as little real estate as possible, because large inductor/transformer area induces large parasitic capacitance between the on-chip inductor/transformer and the substrate that not only picks up undesired noise from other parts of circuit through a silicon substrate but also severely limits the self-resonating frequency of the on-chip inductor and transformer.